Capacitors are used in many integrated circuit applications, such as for example, switched capacitors in analog-to-digital converters (ADCs). There are many ways to implement integrated circuit capacitors. The “fringe” capacitor is one type of integrated circuit capacitor that is widely used because it provides good capacitance density.
Two desirable attributes of many integrated circuit designs, including ADCs are low power consumption and/or high speed operation. Therefore, it would be desirable to size the capacitors used in ADCs as small as possible. However, for fringe capacitors used in switched capacitor circuits, noise and mismatch constraints limit the minimum capacitance value that can be used. The noise constraint is determined by MOSFET thermal switching noise and the mismatch constraint is determined by physical variations in the metal used to form the fringe capacitor. Both of these constraints are process dependent, with the mismatch constraint typically dominating the noise constraint and requiring a larger capacitance value than the noise constraint, thus increasing power consumption and/or reducing speed of the integrated circuit.
Therefore, there is a need to decrease the capacitance value of a fringe capacitor used in a switched capacitor integrated circuit design.